The RF Interlock System oversees preventing damage to the RF equipment within each cell and RF chain and will also prevent any damage to other equipment related to the RF station.
The interlock system monitors all the sensors in the RF cell and allows operation only when all signals are ok. The signals that are monitored are divided into fast signals and slow signals depending on the required response time. The fast interlock system is implemented in FPGA based on MTCA.4 and for the slow interlock system, the times provided by the PLC technology is enough.
RF Drive and/or HV Modulator interruption will be carried out depending on the failure condition.
The system must keep a record of n last relevant interlock events and its timestamp in order to allow post-mortem analysis. Moreover, the interlock functions must be performed independently of the RF control functions and should not be affected by any software affairs.