Low Level RF system
The LLRF system picks up a signal or several signals from the cavity pick-up and a signal from the phase reference line system to calculate the required amplitude and phase in the cavity. The LLRF system also tunes the cavities via a tuning control, either mechanically or via the cavity temperature.
The LLRF system is based on ΜTCA.4 standard, since it fulfils requirements on flexibility, size and options for redundancy.
The ΜTCA.4 is a standard developed especially for the physics community and is a highly modular system. It consists of a crate with modules in pairs, where one module is
facing front and one back. Thus, sensitive cabling can be routed to the back of the crate
where it will be better protected, and the front panels used for monitoring and service. The ΜTCA.4 LLRF implementation requires several modules:
The LLRF system for ESS will be based on digital control structure, where the automatic control algorithms is executed in an FPGA. The input from the cavity is down-mixed and the IF-signal is sampled in the ADC. The output from the FPGA is converted to an analog signal in the DAC, and up-mixed to the RF-frequency with the same LO as used by the down-mixer. This implies a minimization on phase drifts and frequency errors from the LO, which is synthesized from the clock signal of the timing system.
The distribution system consists of the following main part:
- MCH: controller for the crate.
- CPU: running Linux and an implementation of the control box.
- Timing receiver.
- ADC and DAC.
- Slow/Fast tuner interface.
The master oscillator box provides the RF frequencies needed to generate the phase reference and the master clock of the accelerator.
ESS Bilbao has designed a prototype for broadband performance rather than optimized for a single frequency, which will be able to provide a broad range of Local Oscillator (LO) and Clock frequencies for both 352 and 704 MHz LLRF systems, while using either 352 or 704 MHz reference. Thus, different intermediate frequencies, clock frequencies and quasi-IQ sampling parameters could be tested and eventually validated.
The synthesizer is locked to an external reference (either 352.21 or 704.42 MHz) and generates the LO frequency. This is amplified and split to provide two identical LO outputs.
The clock divider provides also two outputs, by dividing either the reference frequency or the LO frequency, selectable by a high isolation RF switch.